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product overview address spaces addressing modes memory map sam47 instruction set
s3c7574/p7574 (p reliminary s pec ) product overview 1- 1 1 product overview overview the s3c7574 single-chip cmos microcontroller has been designed for high perfo rmance using samsung's newest 4- bit cpu core, sam47 ( samsung arrangeable microcontrollers). with features such as, dtmf generator, lcd direct drive capability, 8-bit timer/counter, and watch timer , the s3c7574 offers an excellent design solution for a wide variety of telecommunication applications that require lcd functions. up to 15 pins of the 64 -pin qfp package , it can be dedicated to i/o. four vectored interrupts provide fast response to internal and external events. in addition, the s3c7574 's advanced cmos technology provides for low power consumption and a wide operat ing voltage range. otp the s3c7574 microcontroller is also available in otp (one time programmable) version, S3P7574. the S3P7574 microcontroller has an on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the S3P7574 is comparable to s3c7574, both in function and in pin configuration.
product overview s3c7574/p7574 ( preliminary spec ) 1- 2 features memory ? 256 4-bit data ram ? 32 4-bit display ram ? 4096 8-bit rom i/o pins ? input only: 4 pins ? i/o: 11 pins ? ou tput: 8 pins sharing with segment driver outputs lcd controller/driver ? maximum 16-digit lcd direct drive capability ? 32 segment, 4 common pins ? display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-bit basic timer ? programmable interval timer ? watchdog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output watch timer ? real-time and interval time measurement ? four frequency outputs to buz pin ? clock source generation for lcd bit sequential carrier ? support 16-bit serial data transfer in arbitrary format dtmf generator ? 16 dual-tone frequencies for tone dialing applications (only 3.58 mhz) interrupts ? t wo internal vectored interrupts ? two external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main or sub system oscillation stops) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 2.0 v to 5.5 v at 4.19 mhz ? 1.8 v to 5.5 v at 3 mhz package type ? 64 -qfp -1420f ? 64-qfp-1414
s3c7574/p7574 (p reliminary s pec ) product overview 1- 3 block diagram instruction register arithmetic and logic unit instruction decoder internal interrupts interrupt control block clock 4-kbyte program memory x in xt in program counter program status word 288 x 4-bit data memory 8-bit timer counter 0 x out xt out reset int0, int1, int2 p8.0-p8.7/ seg24-seg31 output port 8 i/o port 6 stack pointer dtmf generator basic timer watch timer p2.3/buz lcd driver/ controller i/o port 3 i/o port 2 input port 1 p1.3/tcl0 p2.0/tclo0 p6.0-p6.3/ ks0-ks3 p3.0/lcdck p3.1/lcdsy p3.2 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p1.0/int0 p1.1/int1 p1.2/int2 p1.3/tcl0 bias v lc0 -v lc2 lcdck/p3.0 lcdsy/p3.1 seg0-seg23 com0-com3 seg24-seg31 /p8.0-p8.7 dtmf figure 1 -1 . s3c7574 simplified block diagram
product overview s3c7574/p7574 ( preliminary spec ) 1- 4 pin assignments com0 com1 com2 com3 bias v lc0 v lc1 v lc2 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 s3c7574 (64-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 64 63 62 61 60 59 58 57 56 55 54 53 52 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 dtmf p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 figure 1 -2 . s3c7574 64- qfp pin assignment
s3c7574/p7574 (p reliminary s pec ) product overview 1- 5 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 v dd v ss x out x in test xt in xt out reset s3c7574 (64-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 dtmf p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1-3. s3c7574 64-qfp pin assignment
product overview s3c7574/p7574 ( preliminary spec ) 1- 6 pin descriptions table 1 - 1. s3c7574 pin descriptions pin name pin type description number share pin reset value circuit type p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 17 18 19 20 int0 int1 int2 tcl0 input a-4 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 21 22 23 24 tclo0 ? clo buz input d p3.0 p3.1 p3.2 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 25 26 27 lcdck lcdsy ? input d p6.0?p6.3 i/o 4-bit i/o ports. pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 29?32 ks0?ks3 input d p8.0?p8.7 o output port for 1-bit data (for use as cmos driver only) 33?40 seg24? seg31 output h-1 dtmf o dtmf output 28 output g-6 seg0?seg23 o lcd segment signal output 41?64 ? output h seg24?seg31 o lcd segment signal output 33?40 p8.0?p8.7 output h-1 com0?com3 o lcd common signal output 1?4 ? output h v lc0 ?v lc2 ? lcd power supply. built-in voltage dividing resistors 6?8 ? ? ? bias ? lcd power control 5 ? ? ? lcdck i/o lcd clock output for display expansion 25 p3.0 input d
s3c7574/p7574 (p reliminary s pec ) product overview 1- 7 table 1 - 1. S3P7574 pin descriptio ns (continued) pin name pin type description number share pin reset value circuit type lcdsy i/o lcd synchronization clock output for lcd display expansion 26 p3.1 input d tcl0 i external clock input for timer/counter 0 20 p1.3 input a-4 tclo0 i/o timer/counter 0 clock output 21 p2.0 input d int0 int1 i external interrupt. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 17 18 p1.0 p1.1 input a-4 int2 i quasi-interrupt with detection of rising edge signals. 19 p1.2 input a-4 ks0?ks3 i/o quasi-interrupt input with falling edge detection. 29?32 p6.0?p6.3 input d clo i/o cpu clock output 23 p2.2 input d buz i/o 2, 4, 8 or 16 khz frequency output for buzzer sound with 4.19 mhz main system clock or 32.768 khz subsystem clock. 24 p2.3 input d x in , x out ? crystal, ceramic or rc oscillator pins for main system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 11, 12 ? ? ? xt in , xt out ? crystal oscillator pins for subsystem clock. (for external clock input, use xt in and input xt in ?s reverse phase to xt out ) 14, 15 ? ? ? v dd ? main power supply 9 ? ? ? v ss ? ground 10 ? ? ? reset ? reset signal 16 ? input b test ? test signal input (must be connected to v ss ) 13 ? ? ? note: pull-up resistors for all i/o ports automatically disabled if they are configured to output mode.
product overview s3c7574/p7574 ( preliminary spec ) 1- 8 pin circuit p-channel n-channel in v dd figure 1 -4 . pin circuit type a schmitt trigger v dd resistor enable in pull-up resistor figure 1 -5 . pin circuit type a-4 (p1) p-ch n-ch v dd out output disable data figure 1 -6 . pin circuit type c p-channel i/o output disable data circuit type c resistor enable v dd pull-up resistor circuit type a figure 1 -7 . pin circuit type d (p2, p3, and p6)
s3c7574/p7574 (p reliminary s pec ) product overview 1- 9 v lc1 v lc0 out lcd segment/ common data v lc2 figure 1 -8 . pin circuit type h (seg/com) v lc0 v dd out lcd segment/ & port 8 data v lc2 v lc1 figure 1 -9 . pin circuit type h-1 (p8) in v dd schmitt trigger figure 1 -10 . pin circuit type b (reset) disable dtmf out + - figure 1-11. pin circuit type g-6 (dtmf)
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 1 14 electrical data overview in this section, information on s3c7574 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl 0 timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply vol tage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 output current high i oh one i/o p ort active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) + 15 (note) total value for ports 2 and 3 + 60 (peak value) + 20 (note) total value for port 6 + 50 + 2 0 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 note: the values for output current low ( i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 1, 6, and reset 0.8 v dd ? v dd v ih3 x in , x out , and xt in v dd ? 0.1 ? v dd input l ow v il1 ports 2 and 3 ? ? 0.3 v dd v v oltage v il2 ports 1, 6 and reset ? ? 0.2 v dd v il3 x in , x out , and xt in ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 2, 3 , 6 and bias v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 only v dd ? 2.0 ? ?
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 3 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 2 , 3, 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 a ; port 8 only ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out and xt in 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , and xt in ? ? ? 3 i lil2 v in = 0 v x in , x out , and xt in ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? 3 pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 6 25 50 100 k w v dd = 3 v 50 100 200 r l2 v in = 0 v; v dd = 5 v reset 100 250 400 v dd = 3 v 200 500 800 lcd voltage dividing r esistor r lcd t a = 25 c 100 150 200 com output r com v dd = 5 v - 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 ?com i ) i o = ua (i = 0?3) ? 45 90 mv
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 4 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units seg output voltage deviation v ds v dd = 5 v (v lc0 ?eg i ) i o = 15 ua ( i = 031) ? 45 90 mv v lc0 output voltage v lc0 t a = 25 c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 5 table 14- 2. d.c. electrical characteristics (con tinued ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) (dtmf on) main operating: v dd = 5 v 10 % cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22 p f 3.58 mhz ? 3.9 7.0 ma v dd = 3 v 10 % 2.0 4.0 i dd2 (2) (dtmf off) main i dle mode; v dd = 5 v 10 % cpu = fx/4 scmod =0000b c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 3.58 mhz ? 3.5 2.5 8.0 5.0 v dd = 3 v 10 % 6.0 mhz 3.58 mhz 1.6 1.2 4.0 2.3 i dd3 (2) main operating: v dd = 5 v 10 % cpu = fx/4, scmod = 0000b c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 3.58 mhz ? 1.0 0.9 2.5 1.8 v dd = 3 v 10 % 6.0 mhz 3.58 mhz 0.5 0.4 1.0 0.8 i dd4 sub operating: v dd = 3 v 10 % cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 15 30 m a i dd5 sub idle mode: v dd = 3 v 10 % cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd6 stop mode; v dd = 5 v 10 % v dd = 3 v 10 % scmod = 0000b xt in = 0 v ? 2.0 0.6 5 3 stop mode; v dd = 5 v 10 % v dd = 3 v 10 % scmod = 0100b 0.2 0.1 3 2
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 6 table 14- 2. d.c. electrical characteristics (con tinued ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units row tone level v row v dd = 2.0 to 5.5 v rl = 12 k w ; temp = - 30 to 60 c - 16.0 -14.0 -12.0 dbv ratio of column to row tone db cr v dd = 2.0 to 5.5 v rl = 12 k w ; temp = - 30 to 60 c 1 2 3 db distortion (dual tone) thd v dd = 2.0 to 5.5 v 1 mhz band r l = 12 k w ; temp = - 30 to 60 c ? ? 5 % notes: 1. d.c. electrical values for supply current (i dd1 to i dd7 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3 . when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main- system clock oscillation stops by the stop instruction.
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 7 table 14- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator x in x out r frequency (1) v dd = 5 v r = 20 k w , v dd = 5 v r = 39 k w , v dd = 3 v 0.4 - 2.0 1.0 2 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 8 table 14- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 9 table 14- 5. input/ o utput capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 14-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 0.95 ? 64 with subsystem clock ( fxt) 114 122 125 tcl0 input f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5 v 1 m hz tcl0 i nput h igh, t tih0 , t til0 v dd = 2.7 v to 5.5 v 0.48 ? ? m s low w idth v dd = 1.8 v to 5 .5 v 1.8 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, k s 0 ? k s 3 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock ( fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 10 1.5 mhz cpu clock 500 khz 250 khz 15.6 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 750 khz 4.19 mhz 1.0475 mhz figure 14- 1. standard operating voltage range table 14-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.5 ? 6.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 1 m a release signal set time t srel normal operation 0 ? ? m s oscillator stabilization wait t wait released by reset ? 2 17 / fx ? ms time (1) released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid in stability during oscillator start- up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 14- 2. stop mode release timing when initiated b y reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14- 3. stop mode release timing when initiated b y interrupt request
electrical data s3c7574/p7574 (p reliminary s pec ) 14- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in and x t in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14- 5. clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14- 6. clock timing measurement at x t in
s3c7574/p7574 (p reliminary s pec ) electrical data 14- 13 tcl0 t tih0 t til0 1/f ti0 0.8 v dd 0.2 v dd figure 14- 7. tcl 0 timing reset t rsl 0.2 v dd figure 14- 8. input timing for reset reset signal int0, 1, 2, 4, ks0 to ks3 t inth t intl 0.8 v dd 0.2 v dd figure 14- 9. input timing for external interrupts and quasi-interrupts
s3c7574/p7574 (p reliminary s pec ) mechanical data 15-1 15 mechanical data overview the s3c7574 microcontroller is available in a 64 -pin qf p package ( samsung: 64-qfp-1420f and 64-qfp- 1414). package dimensions are shown in figure 15-1 and figure 15-2. 64-qfp-1420f #64 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 1.00 (1.00) 0.40 + 0.10 - 0.05 note : dimensions are in millimeters. 0.80 0.20 0.10 max 0.15 + 0.10 - 0.05 0-8 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 max figure 15-1. 64 -qfp-14 20f package dimensions
mechanical data s3c7574/p7574 (p reliminary s pec ) 15 ? 2 64-qfp-1414 #64 note : dimensions are in millimeters. 14.00 0.20 17.20 0.30 14.00 0.20 17.20 0.30 0.10 max #1 0.80 0.15 + 0.10 - 0.05 0-8 0.80 0.20 0.05 min 2.60 0.10 2.80 max 0.35 0.10 (1.00) figure 15-2. 64-qfp-1414 package dimensions.
s3c7574/p7574 (p reliminary s pec ) S3P7574 otp 16- 1 16 S3P7574 otp overview the S3P7574 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c7574 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the S3P7574 is fully compatible with the s3c7574, both in function and in pin configuration. because of its simple programming requirements, the S3P7574 is ideal for use as an evaluation chip for the s3c7574.
S3P7574 otp s3c7574/p7574 (p reliminary s pec ) 16- 2 com0 com1 com2 com3 bias v lc0 sdat /v lc1 sclk /v lc2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p1.0/int0 p1.1/int1 p1.2/int2 S3P7574 (64-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 64 63 62 61 60 59 58 57 56 55 54 53 52 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 dtmf p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 figure 16-1. S3P7574 pin assignments (64-qfp)
s3c7574/p7574 (p reliminary s pec ) S3P7574 otp 16- 3 com0 com1 com2 com3 bias v lc0 sdat /v lc1 sclk /v lc2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset S3P7574 (64-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/tcl0 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz p3.0/lcdck p3.1/lcdsy p3.2 dtmf p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24/p8.0 seg25/p8.1 seg26/p8.2 seg27/p8.3 seg28/p8.4 seg29/p8.5 seg30/p8.6 seg31/p8.7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 16-2. S3P7574 pin assignments (64-qfp)
S3P7574 otp s3c7574/p7574 (p reliminary s pec ) 16- 4 table 16-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function v lc1 sdat 7 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. v lc2 sclk 8 i/o serial clock pin. input only pin. test v pp (test) 13 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 16 i chip initialization v dd /v ss v dd /v ss 9/10 i logic power supply pin. v dd should be tied to + 5 v during programming. table 16-2. comparison of S3P7574 and s3c7574 features characteristic S3P7574 s3c7574 program memory 4-kbyte eprom 4-kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 64 qfp 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P7574, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem mem address (a15?a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3c7574/p7574 (p reliminary s pec ) S3P7574 otp 16- 5 table 16-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 1, 6, and reset 0.8 v dd ? v dd v ih3 x in , x out , and xt in v dd ? 0.1 ? v dd input l ow v il1 ports 2 and 3 ? ? 0.3 v dd v v oltage v il2 ports 1, 6 and reset ? ? 0.2 v dd v il3 x in , x out , and xt in ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 2, 3 , 6 and bias v dd ?1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 only v dd ? 2.0 ? ? output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 2 , 3, 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 a ; port 8 only ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out and xt in ? ? 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , and xt in ? ? ? 3 m a i lil2 v in = 0 v x in , x out , and xt in ? ? ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? ? ? 3
S3P7574 otp s3c7574/p7574 (p reliminary s pec ) 16- 6 table 16-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 6 25 50 100 k w v dd = 3 v 50 100 200 r l2 v in = 0 v; v dd = 5 v reset 100 250 400 v dd = 3 v 200 500 800 lcd voltage dividing r esistor r lcd t a = 25 c 100 150 200 com output r com v dd = 5 v - 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 ?com i ) i o = 15 ua (i = 0?3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 ?seg i ) i o = 15 ua (i = 0?31) ? 45 90 mv v lc0 output voltage v lc0 t a = 25 c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2
s3c7574/p7574 (p reliminary s pec ) S3P7574 otp 16- 7 table 16-4 . d.c. electrical characteristics (con tinued ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) main operating: v dd = 5 v 10 % cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22 p f 6.0 mhz 4.19 mhz ? 3.5 2.5 8 5.5 ma v dd = 3 v 10 % 6.0 mhz 4.19 mhz 1.6 1.2 4 3 i dd2 (2) main i dle mode; v dd = 5 v 10 % cpu = fx/4 scmod =0000b c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 1 0.9 2.5 2 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.0 0.8 i dd3 sub operating: v dd = 3 v 10 % cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 15 30 m a i dd4 sub i dle mode: v dd = 3 v 10 % cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd5 stop mode: v dd = 5 v 10 % cpu=fxt/4, scmod = 1101b ? 0.5 3 i dd 6 (3) stop mode: v dd = 5 v 10% cpu = fx/4, scmod = 0100b notes: 1. d.c. electrical values for supply current (i dd1 to i dd6 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3 . when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main- system clock oscillation stops by the stop instruction.
ks57p2304 otp ks57c2302/c2304/p23 04 microcontroller 16- 8 1.5 mhz cpu clock 500 khz 250 khz 15.6 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 750 khz 4.19 mhz 1.0475 mhz figure 16-3 . standard operating voltage range i ol (ma) 35.00 .0000 .0000 3.500/div 2.000 v ol (v) .2000/div v dd = 4.5 v v dd = 3.3 v v dd = 5.5 v v dd = 2.2 v figure 16-4. port 2 i ol vs v ol curve

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